Sundance SMT351T - Manual (Page 17)

SMT351T User Guide Page 17 of 37 Last Edited: 04/09/2009 11:26:00
The FPGA LVDS DIFF_TERM standard should be used instead of the DCI terminations when
LVDS standard is selected.
DCI terminations are only available when a 2.5v standard is selected.
The LVDS Clock signals are also in these banks.
In LVTTL mode, all LVTTL signals are connected to a 3.3V powered FPGA bank.
(Link selectable by jumper JP2).
In case the SLB bus is to be used with a mezzanine, the SLB voltage
level must be set according to the mezzanine fitted on the module.
4.2.11 TIM Connectors
TIM connectors provide 4 communication links (Comports) and a Global Bus to the FPGA.
The comports which are available on the SMT351T are CP0, CP1, CP3, and CP4.
They allow interfacing to Sundance TIM modules or to a Host PC providing that you
implement a Comport Interface inside the FPGA. (See
X90H90H
2.1
X
)
The Comport interface is available in Sundance SMT6500 support package.
The FPGA io banks hosting the Comport signals are powered using Vcco = 3.3v.
The TIM connectors also provide power/ground, reset and various control signals.
References and specifications for these connectors are available in
H28H28HHTU
TI TIM specification &
user’s guide
UTHH
4.2.12 DIP Switches
One four-position DIP switch is connected to the CPLD to provide control over the selection of
the configuration bitstream source and a special reset feature called “TIM Confign”.
SW1 pos 4 TIM Config
ON ENABLED
OFF DISABLED
Table 1: DIP switch SW1 position for special reset feature