Sundance SMT351T - Manual (Page 16)

SMT351T User Guide Page 16 of 37 Last Edited: 04/09/2009 11:26:00
Alternative part numbers, fully compatible can be fitted depending on availability at time of
order.
4.2.9 Sundance Rocket io Serial Link
Sundance boards can be interconnected using RSL connectors located on the front and back of
the board. The SMT351T has four connectors in total (two at the front and two at the back).
The boards connected via RSL use the RSL protocol to communicate. Refer to the Sundance
Help File for more details.
The underlying design of the RSL uses the MGT of the FPGA to transfer the data. Each FPGA
has a different amount or MGTs. Some FPGAs do not have any MGTs; boards using these
cannot use the RSL protocol.
The speed of the RSL depends on the frequency at which the MGTs are clocked. Sundance
uses 125Mhz, allowing data rate of 2.5Gbits/s per MGT.
Depending on the FPGA fitted on the SMT351T up to 16 RSL links may be available.
The LX50T and SX50T FPGAs provide 12 links
The LX110T and SX95T FPGAs provide 16 links.
4.2.10 Sundance Low voltage Bus
The SLB bus is used to extend the functionality of the SMT351T by connecting to it a daughter
board.
There are different types of daughter boards. Some provide ADCs, some DACs or a
combination of both.
Sundance provides examples and reference design combining the SMT351T to daughter
boards. These examples are usually designed with 3L Diamond tools.
Electrical details
Typically, this is an LVDS bus comprising data (2 x 16 bit buses, I & Q), clock, and control
signals.
Nevertheless, the SLB lines can also be used for single ended signalling.
They allow interfacing to Sundance mezzanine modules providing that you implement an SLB
interface in the FPGA. (See
X89H89H
2.1
X
)
They allow interfacing to the outside world by implementing your own LVDS interface in the
FPGA.
In LVDS mode, all LVDS data pins (both I and Q) are connected to a 2.5V powered FPGA
bank (link selectable by jumper JP2).