Sundance SMT351T User Manual
Page 3
SMT351T User Guide
Page 3 of 37
Last Edited: 04/09/2009 11:26:00
Table of Contents
1
Introduction ................................................................................................................ 6
2
Related Documents..................................................................................................... 7
2.1
Referenced Documents .............................................................................................7
2.2
Applicable Documents ..............................................................................................7
3
Acronyms, Abbreviations and Definitions ................................................................. 7
3.1
Acronyms and Abbreviations ...................................................................................7
3.2
Definitions .................................................................................................................7
4
Functional Description ............................................................................................... 9
4.1
Block Diagram...........................................................................................................9
4.2
Module Description.................................................................................................10
4.2.1
FPGA...................................................................................................................10
4.2.2
CPLD...................................................................................................................10
4.2.3
FLASH MEMORY..............................................................................................10
4.2.4
JTAG Header......................................................................................................11
4.2.5
FPGA Configuration schemes............................................................................11
4.2.6
FPGA Reset Scheme...........................................................................................12
4.2.7
FPGA Bitstream formatting ..............................................................................14
4.2.8
DDR2SDRAM .....................................................................................................14
4.2.9
Sundance Rocket io Serial Link ........................................................................16
4.2.10
Sundance Low voltage Bus ................................................................................16
4.2.11
TIM Connectors..................................................................................................17
4.2.12
DIP Switches ......................................................................................................17
4.2.13
Available clocks ..................................................................................................18
4.2.14
LEDs ...................................................................................................................20
4.2.15
Performance........................................................................................................20
4.3
Interface Description ..............................................................................................20
4.3.1
Power Budget .....................................................................................................20
5
Footprint ....................................................................................................................22
5.1
Top View..................................................................................................................22
5.2
Bottom View............................................................................................................23
6
Pinout.........................................................................................................................24
6.1
FPGA Pin allocation by bank .................................................................................24
6.2
SHB..........................................................................................................................33
6.3
SLB ..........................................................................................................................33
6.4
JTAG........................................................................................................................34