Sundance SMT351T - Manual (Page 11)

SMT351T User Guide Page 11 of 37 Last Edited: 04/09/2009 11:26:00
4.2.4 JTAG Header
The JTAG header is compatible with Xilinx
H21H21HHTU
Parallel-IV
UTHH
cable signals.
The header is a custom header that plugs onto a custom cable that must be ordered at time from
Sundance.
This cable then plugs into the Xilinx parallel cable pod.
It supports
T
code download (for the FPGA), FPGA configuration, Hardware and Software
Debugging tools for the Virtex-5.
This cable connects the parallel port/USB port of an engineer's Workstation/PC to the JTAG
chain of the SMT351T Module.
All the Xilinx devices from block1 are chained and accessible via this JTAG header.
4.2.5 FPGA Configuration schemes
Different schemes are available to provide maximum flexibility in systems where the
SMT351T is involved:
The FPGA configuration bitstream source is
• On Comport 3:
The CPLD is connected to the Comport 3 link of the SMT351T TIM connector. (See block1).
A switch is used to select Comport 3 as the link that will be used to receive the bitstream.
The CPLD allows for FPGA configuration in slave SelectMAP mode.
• Using the on-board Flash memory.
The CPLD monitors the configuration data between the Flash and the FPGA.
The FPGA configuration is operated in Slave SelectMap mode.
A switch is used to select the Flash as the source for the configuration bitstream.
• Using the on-board JTAG header and Xilinx JTAG programming tools.
The JTAG header is a
H22H22HHTU
Parallel-IV
UTHH
Header.
Note: Using JTAG to configure the FPGA bypasses the CPLD which controls configuration.
The following section describes the CPLD role and the reset scheme used.
As the CPLD is bypassed when JTAG is used to configure the FPGA, it is necessary to adopt
one of the three following ways: