Measurement Computing PCI-DAS4020/12 - Manual (Page 22)

22
Chapter 5
Specifications
Typical for 25 °C unless otherwise specified.
Specifications in italic text are guaranteed by design.
Analog input
Table 1. Analog input specifications
A/D converter type AD9225, 25 MSPS pipelined A/D
Resolution 12-bits
Programmable ranges ±5 V, ±1 V
Number of channels 4 single-ended, independent ADC’s per channel
Connection 4 independent BNC
Bandwidth 17 MHz typical
Coupling DC
Input leakage current 2 uA typ, 10 uA max
Input impedance 1.5 Mohm typ, or 50 ohm, selectable
(coaxial cable termination)
Absolute maximum input voltage ±15 V
Timing and throughput
Table 2. Timing and throughput specifications
Simultaneous sampling Software selectable option - 1, 2, or 4 channels
A/D Convert clock source Internal:
 On-card crystal oscillator
 Frequency: 40 MHz
 Frequency accuracy: 50% duty cycle, 50 ppm
External:
 Trig/Ext Clk BNC, or A/D External Clock on the 40-pin connector
 24-bit internal pre-scale counter (min pre-scale = 2)
 Clock Rate: 40 MHz max, 2 kHz min
 Duty Cycle: 50% ± 5%
A/D Gate source Digital: Trig/Ext Clk BNC or A/D Pacer Gate on 40-pin connector
Analog: Any of the four input channels
A/D Gate modes Digital: Programmable active high/low, level/edge
Analog: Above/below reference, positive/negative
Hysteresis, inside/outside window
Resolution: 12-bit
Slew rate: 10V/sec. minimum
A/D Start Trigger (TRIG1) Software: Using a DAQ start command.
Digital: Trig/Ext Clk BNC, A/D Start Trigger In (on the 40-pin connector)
Analog: Any of the four input channels
A/D Stop Trigger (TRIG2) Digital: Trig/Ext Clk BNC, A/D Stop Trigger In (on the 40-pin connector)
Analog: Any of the four input channels
A/D Triggering modes Digital: Programmable rising or falling edge
Analog: Trigger above/below reference
Resolution: 12-bit
Pre-trigger mode Unlimited number of pre-trigger samples, 16 Meg post-trigger samples.
Compatible with both digital and analog trigger/gate options. Data acquisition
initiated via TRIG1. Post-trigger phase initiated via TRIG2.