Artesyn RTM ATCA-F140 Installation and Use (July 2014) - Manual (Page 48)

Functional Description
RTM-ATCA-F140 Installation and Use (6806800M97F) 48
4.7 GPS Connectors
The 1PPS, 10MHz, and TOD inputs for connection to an external GPS receiver are not
supported currently.
4.8 FPGA
The RTM-ATCA-F140 includes a Xilinx XC3S200A-4 FPGA that which performs the following
functions:
 Access to control and status signals on SFP, SFP+, and QSFP+
 Access to control and status signals on the BCM8727, BCM84754, and BCM84740
 Reset handling
 SPI Flash programmer and multiplexing for BCM8727, BCM84754, and BCM84740
configuration
 UART with selectable outputs for the optional GPS receiver (functionality not initially
implemented)
4.8.1 Front-blade Interface
The RTM-ATCA-F140 includes an SPI interface between the front-blade service processor and
the RTM FPGA. There is also an active low interrupt line to the front-blade to request service.
1 Fabric b01 1 FIX_P14
Lane 1
2 Fabric b10 2 FIX_P14
Lane 2
3 Fabric b11 3 FIX_P14
Lane 3
Table 4-10 BCM84740 PHY Addressing (continued)
PHY
Address
High Bits
Channel Source
PHY
Address
Low Bits
PHY
Address
Switch Port
QSFP+
Port Management
Channel