Aplex Technology OPC-5127 - Manual (Page 41)

OPC-5XX7 User Manual 41
By SPD (DRAM timing is set automatically according to memory SPD data)
When selecting Manual, the following five items are configurable; when selecting By SPD, the
following five items are not configurable.
CAS Latency Time
Once a SDRAM is installed, the clock latency will be determined by DRAM clock settings. The
options are: 5, 4, 3 and Auto.
DRAM RAS-to-CAS Delay
You may set the delay period between CAS and RAS signal for DRAM read & write or refreshing.
Shorter delay means quicker response, while longer delay means more stable performance. Options
are: 2, 3, 4, 5, 6 and Auto.
DRAM RAS Precharge
If number of cycles is not sufficient enough to ensure that RAS saves its instructions before
DRAM refreshing, it may cause incomplete refreshing and the DRAM will fail to maintain its data.
Faster precharge means quicker response, while slower precharge means more stable performance.
This item is only valid when a SDRAM is installed.
Options are: 2, 3, 4, 5, 6 and Auto.
Precharge Delay (t RAS)
Options are: Auto and 4~15.
System Memory Frequency
Options are: Auto, 533 and 667(MHz).
SLP_S4# Assertion Width
Four options are available: 4 to 5 Sec.
3 to 4 Sec.
2 to 3 Sec.
1 to 2 Sec.
System BIOS Cacheable
If set to Enabled, the feature will enable the caching of BIOS ROM at F0000h-FFFFFh for better
system performance. However, if any program writes into this memory area, it will result in a system
error. Options are: Enabled and Disabled.
Video BIOS Cacheable
If set to Enabled, the feature will enable the caching of video BIOS ROM for better system
performance. However, if any program writes into this memory area, it will result in a system error.
Options are: Enabled and Disabled.