Altera Transceiver Signal Integrity - Manual (Page 22)

6–4 Chapter 6: Stratix IV GX Transceiver Signal Integrity Demonstration
Running the Demonstration Application and Test Designs
Transceiver Signal Integrity Development Kit, December 2011 Altera Corporation
Stratix IV GX Edition User Guide
c For operating system stability, keep the USB cable connected and the board
powered ON when running the demonstration application.
The following list defines the analog setting parameters in the control panel window:
Resets
The following list describes the available resets:
1 After the System Reset is asserted, the DataChk Status may show unsynced for some
channels due to the asynchronous nature of the reset. Asserting the Data Patrst
synchronizes the error checker to the transmitted data.
Help
The Help button displays the image of the Stratix IV signal integrity board and also
highlights the channel locations and their data rates based on the .sof loaded.
Power Down
Turn on Powerdown to power down the transceiver block.
Serial Loopback
Serial loopback is available for all the channels and can be controlled during run time.
After the serial loopback status in the interface changes, the DataChk Status field
may show unsynced for some channels due to the asynchronous nature of the serial
loopback signal. The Data Patrst should be asserted in this case to synchronize the
error checker with the transmitted data.
Table 6–2. Jumper Header Connections (1)
Jumper Header Connection
VCCHTX (Volt)
Jumper Header Connection
VCCA_L/R (Volt)
Pins 1 and 2 1.4 V Pins 2 and 3 3.0 V
Note to Table 6–2 :
(1) Before you power up the board, specify the VCCHTX and the VCCA jumper settings.
Table 6–1.
Parameter Description
VOD differential output driver voltage.
EQ equalization.
Gain DC gain.
PE
preemphasis/deemphasis.
pre, 1stpost, and 2ndpost settings represent different taps.
Table 6–2.
Reset Description
System Reset for the transceiver.
Error Reset for all the error counters to zero.