Altera Cyclone V E FPGA - Manual (Page 35)

Appendix A: Programming the Flash Memory Device A–5
Restoring the MAX V CPLD to the Factory Settings
December 2014 Altera Corporation Cyclone V E FPGA Development Kit
User Guide
f To ensure that you have the most up-to-date factory restore files and information
about this product, refer to the
Cyclone V E FPGA Development Kit page of the Altera
website.
Restoring the MAX V CPLD to the Factory Settings
This section describes how to restore the original factory contents to the MAX V
CPLD on the FPGA development board. Make sure you have the Nios II EDS
installed, and perform these steps:
1. Set the board switches to the factory default settings described in “Factory Default
Switch Settings” on page 4–2 .
1 DIP switch SW2.1 includes the MAX V device in the JTAG chain.
2. Launch the Quartus II Programmer.
3. Click Auto Detect.
4. Click Add File and select
dir>\kits\cycloneVE_5cefa7f31_fpga\factory_recovery\max5.pof.
5. Turn on the Program/Configure option for the added file.
6. Click Start to download the selected configuration file to the MAX V CPLD.
Configuration is complete when the progress bar reaches 100%.
f To ensure that you have the most up-to-date factory restore files and information
about this product, refer to the
Cyclone V E FPGA Development Kit page of the Altera
website.