Altera Cyclone V E FPGA - Manual (Page 19)

Chapter 6: Board Test System 6–3
Using the Board Test System
December 2014 Altera Corporation Cyclone V E FPGA Development Kit
User Guide
A GUI appears, displaying the application tab that corresponds to the design running
in the FPGA. The Cyclone V E FPGA development board’s flash memory ships
preconfigured with the design that corresponds to the GPIO, Flash and SSRAM tabs.
1 If you power up your board with the DIP switch SW4.3 in a position other than the
ON (0) position, or if you load your own design into the FPGA with the Quartus II
Programmer, you receive a message prompting you to configure your board with a
valid Board Test System design.
Using the Board Test System
This section describes each control in the Board Test System application.
The System Info Tab
The System Info tab shows board’s current configuration. Figure 6–1 on page 6–1
shows the System Info tab. The tab displays the contents of the MAX V registers, the
JTAG chain, the board’s MAC addresses, the flash memory map, and other details
stored on the board.
The following sections describe the controls on the System Info tab.
Board Information
The Board information controls display static information about your board.
■ Board Name —Indicates the official name of the board.
■ Part P/N —Indicates the part number of the board.
■ Serial number —Indicates the serial number of the board.
■ Factory test version —Indicates the version of the Board Test System currently
running on the board.
■ MAC (J8) —Indicates the MAC addresses for Ethernet port (J8).
■ MAC (J9) —Indicates the MAC addresses for Ethernet port (J9).
■ MAX V ver —Indicates the version of MAX V code currently running on the
board. The MAX V code resides in the dir>\kits\cycloneVE_5cefa7f31_fpga\examples directory. Newer revisions of
this code might be available on the
Cyclone V E FPGA Development Kit page of
the Altera website.