Altera SDK for OpenCL Cyclone V SoC - Manual (Page 9)

• c5soc board
This default board provides access to two DDR memory banks. The hard processor system (HPS)
DDR is accessible by both the FPGA and the CPU. The FPGA DDR is only accessible by the FPGA.
• c5soc_sharedonly board
This board variant contains only HPS DDR connectivity. The FPGA DDR is not accessible. This board
variant is more area efficient because less hardware is necessary to support one DDR memory bank.
The c5soc_sharedonly board is also a good prototyping platform for a final production board with a
single DDR memory bank.
To target this board variant when compiling your OpenCL kernel, include the
--board
c5soc_sharedonly
option in your
aoc
command.
For more information on the
-- board
option of the
aoc
command, refer to the
Compiling a Kernel for a Specific FPGA Board (--board ) section of the Altera SDK for
OpenCL Programming Guide.
Related Information
Compiling a Kernel for a Specific FPGA Board (--board )
Design Considerations
When designing your OpenCL kernel and host program for execution on the Cyclone V SoC
Development Kit, factor in design considerations such as shared memory usage and FPGA area
optimization.
Shared memory is the preferred memory for FPGA kernels. For information on how to allocate and use
shared memory, refer to the Allocating Shared Memory for OpenCL Kernels Running on SoCs section of
the Altera SDK for OpenCL Programming Guide.
The Cyclone V SoC FPGA on the Cyclone V SoC Development Kit is not considered a large FPGA.
However, if you structure your kernel code in a way that optimizes hardware usage, it can provide
sufficient hardware resources to implement complex computations. Altera recommends that you consult
the Altera SDK for OpenCL Best Practices Guide to get a good understanding of the Altera Offline
Compiler (AOC). In addition, refer to the Strategies for Optimizing FPGA Area Usage section of the Altera
SDK for OpenCL Best Practices Guide for tips on area optimization.
Related Information
• Allocating Shared Memory for OpenCL Kernels Targeting SoCs
• Strategies for Optimizing FPGA Area Usage
• Altera SDK for OpenCL Best Practices Guide
1-6 Design Considerations
OCL006-15.0.0
2015.05.04
Altera Corporation Altera SDK for OpenCL Cyclone V SoC Getting Started Guide
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