Altera SDK for OpenCL Cyclone V SoC User Manual
Page 8
Figure 1-2: Overview of AOCL and Board Setup
Review prerequisites
Download installers from altera.com
(Quartus II software, Cyclone V + Stratix V
device support, AOCL, SoC EDS)
Install Quartus II software,
Cyclone V + Stratix V device support,
AOCL, SoC EDS
HW, SW,
OS prereq
satisfied?
Acquire prerequisite
HW, SW, OS
aoc executable
runs?
NO
YES
NO
YES
Legend
Action
Decision
Install Cyclone V SoC
Development Kit
Run hello_world
on FPGA
aocl
diagnose
= PASSED?
YES
NO
Set up Cyclone V Development Kit
1. Write SD card image onto flash card
2. Set DIP switches
3. Terminal Connection
4. Set env. variables and load Linux kernel driver
Connect board to
network
Cyclone V SoC Development Kit Reference Platform Board Variants
The Cyclone V SoC Development Kit Reference Platform (c5soc) includes two board variants.
OCL006-15.0.0
2015.05.04
Cyclone V SoC Development Kit Reference Platform Board Variants
1-5
Altera SDK for OpenCL Cyclone V SoC Getting Started Guide
Altera Corporation
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)