Altera Phase-Locked Loop - Manual (Page 9)

PLL Lock
The PLL lock is dependent on the two input signals in the phase frequency detector. The lock signal is an
asynchronous output of the PLLs.
The number of cycles required to gate the lock signal depends on the PLL input clock which clocks the
gated-lock circuitry. Divide the maximum lock time of the PLL by the period of the PLL input clock to
calculate the number of clock cycles required to gate the lock signal.
Operation Modes
The Altera PLL IP core supports six different clock feedback modes. Each mode allows clock multiplica‐
tion and division, phase shifting, and duty-cycle programming.
The following list describes the operation modes for the Altera PLL IP core:
• Direct mode—the PLL minimizes the feedback path length to produce the smallest possible jitter at the
PLL output. In this mode, the PLL does not compensate for any clock networks.
• Normal mode—the PLL feedback path source is a global or regional clock network, minimizing clock
delay from the input clock pin to the core registers through global or regional clock network.
• Source-Synchronous mode—the data and clock signals arrive at the input pins at the same time. In this
mode, the signals have the same phase relationship at the clock and data ports of any Input Output
Enable register.
• External Feedback mode—the PLL compensates for the
fbclk
feedback input to the PLL, thus
minimizing the delay between the input clock pin and the feedback clock pin.
• Zero-Delay Buffer mode—the PLL feedback path is confined to the dedicated PLL external output pin.
The clock port driven off-chip is phase aligned with the clock input for a minimal delay between the
clock input and the external clock output.
• LVDS mode— maintains the same data and clock timing relationship of the pins at the internal
SERDES capture register. This mode compensates for the LVDS clock network delay, plus any delay
difference between the data pin and clock input pin to the SERDES capture register paths. The
compensation mimic path mimics the clock and data delay of the receiver side.
Related Information
• Clock Feedback Modes, Clock Networks and PLLs in Arria V Devices chapter
• Clock Feedback Modes, Clock Networks and PLLs in Cyclone V Devices chapter
• Clock Feedback Modes, Clock Networks and PLLs in Stratix V Devices chapter
Output Clocks
The Altera PLL IP core can generate up to 18 clock output signals for the Stratix V and Arria V devices,
and nine clock output signals for the Cyclone V devices. The generated clock output signals clock the core
or the external blocks outside the core.
You can use the
reset
signal to reset the output clock value to 0 and disable the PLL output clocks.
Each output clock has a set of requested settings where you can specify the value of output frequency,
phase shift, and duty cycle. The requested settings are the settings that you want to implement in your
design.
UG-01087
2015.05.04
PLL Lock 9
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide Altera Corporation
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