Altera Phase-Locked Loop - Manual (Page 10)

The actual frequency is the closest frequency setting (best approximate of the requested settings) that can
be implemented in the PLL circuit.
The output frequencies are not exact when the PLL is in fractional mode. You must be cautious with
appliances that require frequencies to be exact to within less than 0.5 Hz.
For applications that require more precise clock output frequencies, turn on Enable physical output
clock parameters in the parameter editor.
Related Information
• Arria V PLLs, Clock Networks and PLLs in Arria V Devices chapter
• Cyclone V PLLs, Clock Networks and PLLs in Cyclone V Devices chapter
• Stratix V PLLs, Clock Networks and PLLs in Stratix V Devices chapter
Reference Clock Switchover
The reference clock switchover feature allows the PLL to switch between two reference input clocks. Use
this feature for clock redundancy, or for a dual clock domain application such as in a system. The system
can turn on a redundant clock if the primary clock stops running.
Using the reference clock switchover feature, you can specify the frequency for the second input clock,
and select the mode and delay for the switchover.
The clock loss detection and reference clock switchover block has the following functions:
• Monitors the reference clock status. If the reference clock fails, the clock automatically switches to a
backup clock input source. The clock updates the status of the
clkbad
and
activeclk
signals to alert
the event.
• Switches the reference clock back and forth between two different frequencies. Use the
extswitch
signal to manually control the switch action. After a switchover occurs, the PLL may lose lock
temporarily and then regain lock.
PLL-to-PLL Cascading
The Altera 28 nm devices instantiate the Altera PLL IP core to allow cascading for PLLs in normal or
direct mode through the Global Clock (GCLK) network.
If you cascade PLLs in your design, the source (upstream) PLL must have a low-bandwidth setting, while
the destination (downstream) PLL must have a high-bandwidth setting. During cascading, the output of
source PLL serves as the reference clock (input) of the destination PLL. The bandwidth settings of
cascaded PLLs must be different. If the bandwidth settings of the cascaded PLLs are the same, the
cascaded PLLs may amplify phase noise at certain frequencies.
The Altera PLL IP core allows you to choose the following input clock sources to cascade with an
upstream PLL:
•
adjpllin
—for inter-cascading between fracturable fractional PLLs.
•
cclk
—for intra-cascading within fracturable fractional PLLs.
The
cclk
input clock source is not supported in Cyclone V devices.
10 Reference Clock Switchover
UG-01087
2015.05.04
Altera Corporation Altera Phase-Locked Loop (Altera PLL) IP Core User Guide
Send Feedback