Qsf assignments – Altera OCT User Manual
Page 7
Table 3: Termination Interface Signals
Description
Direction
Signal Name
16 bit input port. Receives impedance calibration code for
output termination. Source can only be
seriesterminationcontrol
port from the Altera
OCT megafunction.
Input
seriesterminationcontrol
16 bit input port. Receives impedance calibration code for
input termination. Source can only be
parallelterminationcontrol
port from the
Altera OCT megafunction.
Input
parallelterminationcontrol
QSF Assignments
Arria 10 devices has the following termination related Quartus II Settings File (.qsf) assignments:
• INPUT_TERMINATION
• OUTPUT_TERMINATION
• TERMINATION_CONTROL_BLOCK
• RZQ_GROUP
The following table lists the details of each assignment:
Table 4: QSF Assignments
Details
QSF Assignment
The input/output termination assignment specifies
the termination value in ohm on the pin in
question.
Example
set_instance_assignment -name
INPUT_TERMINATION
set_instance_assignment -name
OUTPUT_TERMINATION
INPUT_TERMINATION
OUTPUT_TERMINATION
Altera Corporation
Altera OCT Megafunction User Guide
7
QSF Assignments
ug-altera_oct
2013.11.29
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)