Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Manual
Page 5
Parameter
Legal Value
Description
Switchover Mode
Automatic
Switchover,
Manual
Switchover, or
Automatic
Switchover
with Manual
Override
Specifies the switchover mode for design application. The IP
supports three switchover modes:
• If you select the Automatic Switchover mode, the PLL
circuitry monitors the selected reference clock. If one
clock stops, the circuit automatically switches to the
backup clock in a few clock cycles and updates the status
signals,
clkbad
and
activeclk
.
• If you select the Manual Switchover mode, when the
control signal,
extswitch
, changes from logic low to
logic high, and stays high for at least three clock cycles,
the input clock switches to the other clock. The
extswitch
can be generated from FPGA core logic or
input pin.
• If you select Automatic Switchover with Manual
Override mode, when the
extswitch
signal is high, it
overrides the automatic switch function. As long as
extswitch
remains high, further switchover action is
blocked. To select this mode, your two clock sources
must be running and the frequency of the two clocks
cannot differ by more than 20%. If both clocks are not on
the same frequency, but their period difference is within
20%, the clock loss detection block will detect the lost
clock. The PLL most likely drops out of lock after the
PLL clock input switchover and needs time to lock again.
Switchover Delay
0–7
Turn on to create two
clkbad
outputs, one for each input
clock. Output signal low indicates the clock is working and
output signal high indicates the clock is not working.
Enable access to PLL
LVDS_CLK/LOADEN
output port
Turn on or
Turn off
Turn on to enable the PLL
LVDS_CLK
/
LOADEN
output port.
Enables this parameter in case the PLL feeds an LVDS
SERDES block with external PLL. For more information,
refer to the Signal Interface Between Altera IOPLL and
Altera LVDS SERDES IP Cores table in the I/O and High
Speed I/O in Arria 10 Devices chapter.
Enable access to the PLL
DPA output port
Turn on or
Turn off
Turn on to enable the PLL DPA output port.
Enable access to PLL
external clock output port
Turn on or
Turn off
Turn on to enable the PLL external clock output port.
Specifies which outclk to be
used as extclk_out[0]
source
C0 – C8
Specifies the
outclk
port to be used as
extclk_out[0]
source.
Specifies which outclk to be
used as extclk_out[1]
source
C0 – C8
Specifies the
outclk
port to be used as
extclk_out[1]
source.
UG-01155
2015.05.04
Altera IOPLL IP Core Parameters - Settings Tab
5
Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide
Altera Corporation