Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core - Manual (Page 3)

Parameter Legal Value Description
Number of Clocks 1–9 Specifies the number of output clocks required for each
device in the PLL design. The requested settings for output
frequency, phase shift, and duty cycle are shown based on
the number of clocks selected.
Specify VCO Frequency Turn on or
Turn off
Allows you to restrict the VCO frequency to the specified
value. This is useful when creating a PLL for LVDS external
mode, or if a specific dynamic phase shift step size is desired.
VCO Frequency (1) —
• When Enable physical output clock parameters is
turned on—displays the VCO frequency based on the
values for Reference Clock Frequency, Multiply Factor
(M-Counter), and Divide Factor (N-Counter).
• When Enable physical output clock parameters is
turned off—allows you to specify the requested value for
the VCO frequency. The default value is 600.0 MHz.
Give clock global name Turn on or
Turn off
Allows you to rename the output clock name.
Clock Name — The user clock name for Synopsis Design Constraints (SDC).
Desired Frequency — Specifies the output clock frequency of the corresponding
output clock port,
outclk[]
, in MHz. The default value is
100.0 MHz. The minimum and maximum values depend on
the device used. The PLL only reads the numerals in the first
six decimal places.
Actual Frequency — Allows you to select the actual output clock frequency from a
list of achievable frequencies. The default value is the closest
achievable frequency to the desired frequency.
Phase Shift units ps or degrees Specifies the phase shift unit for the corresponding output
clock port,
outclk[]
, in picoseconds (ps) or degrees.
Desired Phase Shift — Specifies the requested value for the phase shift. The default
value is 0 ps.
Actual Phase Shift — Allows you to select the actual phase shift from a list of
achievable phase shift values. The default value is the closest
achievable phase shift to the desired phase shift.
Desired Duty Cycle 0.0–100.0 Specifies the requested value for the duty cycle. The default
value is 50.0%.
Actual Duty Cycle — Allows you to select the actual duty cycle from a list of
achievable duty cycle values. The default value is the closest
achievable duty cycle to the desired duty cycle.
(1) This parameter is only available when Enable physical output clock parameters is turned off.
UG-01155
2015.05.04
Altera IOPLL IP Core Parameters - PLL Tab 3
Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide Altera Corporation
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