Figure 2–4 – Altera RAM Initializer User Manual
Page 18
2–6
Confidential—Internal Use Only
Altera Corporation
RAM Initializer (ALTMEM_INIT) Megafunction User Guide
May 2008
MegaWizard Plug-In Manager Page Descriptions
Figure 2–4. RAM Initializer MegaWizard Plug-In Manager [page 4 of 5]
Page 5 of the RAM Initializer MegaWizard Plug-In Manager displays the
types of files to be generated. The Variation file, which is automatically
generated, contains wrapper code in the language you specified on
page 2a. On page 5 of the RAM Initializer MegaWizard Plug-In Manager,
specify the types of files to be generated. You can choose from the
following types of files:
■
Instantiation template file (<function name>_inst.v)
■
Verilog HDL black-box declaration file (<function name>_bb.v)
■
AHDL Include file (<function name>.inc)
■
VHDL component declaration file (<function name>.cmp)
■
Quartus II symbol file (<function name>.bsf)
■
Quartus II IP Advisor file (<function name>.qip)
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)