ADLINK ASD8P-MT1 Series - Manual (Page 25)

ASD8P-MT1 Specification Page 25 of 43
Refer to the PCI Express Card Electromechanical Specification for more details on the functional
requirements for the PERST# signal.
WAKE# Signal
PCI Express M. 2 Cards must implement WAKE# if the card supports either the wakeup function
or the OBFF mechanism. Refer to the PCI Express Card Electromechanical Specification for more
details on the functional requirements for the WAKE# signal.
4.4 SDIO Interface
The M. 2 SDIO interface comprise of the following Standard SDIO signals:
• Four bi-directional Data signals, each capable of data rates up to 100Mbits/Sec (for a total of
400Mbits/Sec)
• One bi-directional CMD signal.
• One Clock signal up to 50MHz
These signals are in accordance to standard SDIO specifications. Refer to the SDIO Specification
for more details on the functional requirements for the SDIO interface signals.
• Electrical
Specifications
• PCI Express M. 2 Specification | 99
• Revision 0. 7a, January 2, 2013
The M. 2 SDIO interface also includes two non-standard signals in support of new features related
to the SDIO interface. This includes the following signals:
• SDIO_Wake# The SDIO_Wake# signal is an output from the device (comms module) to the
platform used to trigger the wake the host and to initiate SDIO interface communication
between the device and the platform. This signal is an open drain output and needs to be
pulled high by the platform to 1. 8V always on.
• SDIO_RESET# The SDIO_RESET# signal is an input to the device from the platform and it is
used to reset the SDIO interface. The signal is 1. 8V at the module input.
Since the SDIO_RESET# and SDIO_WAKE# are not part of the standard SDIO specification, the
timing diagrams shown in Figure 80 and Figure 81 show their expected timing behavior. Table 20
lists the SDIO reset and power-up timing parameters.