ADLINK ASD8P-MT1 Series - Manual (Page 21)

ASD8P-MT1 Specification Page 21 of 43
4 PCI Express
4.1 Interface
The PCI Express interface supports the x1 PCI Express interface (one Lane). A Lane consists of
an input and an output high-speed differential pair. Also supported is a PCI Express reference
clock. Refer to the PCI Express Base Specification for more details on the functional
requirements for the PCI Express interface signals.
Socket 1 pin out has provisions for an additional PCI Express lane indicated by the suffix 1 to the
signal names. These additional PETx1 and PERx1 signal sets can serve as the second Lane to
the original PCI Express interface, or alternatively, they can be complimented with a second set
of REFCLKx1 and a set of Auxiliary Signals on the adjacent Reserved pins to form a complete
second PCI Express x1 interface.
4.2 Auxiliary Signals
The auxiliary signals are provided on the system connector to assist with certain system level
functionality or implementation. These signals are not required by the PCI Express architecture,
but may be required by specific implementations such as PCI Express M. 2 Card. The high-speed
signal voltage levels are compatible with advanced silicon processes. The optional low speed
signals are defined to use the +3. 3V supply, as it is the lowest common voltage available. Most
ASIC processes have high voltage (thick gate oxide) I/O transistors compatible with +3. 3V. The
use of the +3. 3V supply allows PCI Express signaling to be used with existing control bus
structures, avoiding a buffered set of signals and bridges between the buses.
The PCI Express M. 2 Card add-in card and system connectors support the auxiliary signals that
are described in the following sections.
4.3 Reference Clock
The REFCLK+/REFCLK. signals are used to assist the synchronization of the card’s PCI Express
interface timing circuits. Availability of the reference clock at the card interface may be gated by
the CLKREQ# signal as described in section 3. 1. 5. 1, CLKREQ# Signal. When the reference
clock is not available, it will be in the parked state. A parked state is when the clock is not being
driven by a clock driver and both REFCLK+ and REFCLK. are pulled to ground by the ground
termination resistors. Refer to the PCI Express Card Electromechanical Specification for more
details on the functional and tolerance requirements for the reference clock signals.