ADLINK ASD8P-MT1 Series - Manual (Page 22)

Page 22 of 43 ASD8P-MT1 Specification
CLKREQ# Signal
The CLKREQ# signal is an open drain, active low signal that is driven low by the PCI Express M. 2
add-I Card function to request that the PCI Express reference clock be available (active clock state)
in order to allow the PCI Express interface to send/receive data. Operation of the CLKREQ#
signal is determined by the state of the Enable Clock Power Management bit in the Link Control
Register (offset 010h). When disabled, the CLKREQ# signal shall be asserted at all times
whenever power is applied to the card, with the exception that it may be de-asserted during L1 PM
Substates. When enabled, the CLKREQ# signal may be de-asserted during the L1 Link state.
The CLKREQ# signal is also used by the L1 PM Substates mechanism. In this case, CLKREQ#
can be asserted by either the system or add-in card to initiate an L1 exit. See the PCI Express
Base Specification for details on the functional requirements for the CLKREQ# signal when
implementing L1 PM Substates.
Whenever dynamic clock management is enabled and when a card stops driving CLKREQ# low, it
indicates that the device is ready for the reference clock to transition from the active clock state to
a parked (not available) clock state. Reference clocks are not guaranteed to be parked by the
host system when CLKREQ# gets de-asserted and module designs shall be tolerant of an active
reference clock even when CLKREQ# is de-asserted by the module.
The card must drive the CLKREQ# signal low during power up, whenever it is reset, and whenever
it requires the reference clock to be in the active clock state. Whenever PERST# is asserted,
including when the device is not in D0, CLKREQ# shall be asserted.
It is important to note that the PCI Express device must delay de-assertion of its CLKREQ# signal
until it is ready for its reference clock to be parked. The device must be able to assert its clock
request signal, whether or not the reference clock is active or parked, when it needs to put its Link
back into the L0 Link state. Finally, the device must be able to sense an electrical idle break on its
up-stream-directed receive port and assert its clock request, whether or not the reference clock is
active or parked.
The assertion and de-assertion of CLKREQ# are asynchronous with respect to the reference clock.
Add-in cards that do not implement a PCI Express interface shall leave this output unconnected on
the card.
CLKREQ# has additional electrical requirements over and above standard open drain signals that
allow it to be shared between devices that are powered off and other devices that may be powered
on. The additional requirements include careful circuit design to ensure that a voltage applied to
the CLKREQ# signal network never causes damage to a component even if that particular
component’s power is not applied.