ADLINK PCI-7442 - Manual (Page 7)

i
List of Tables.......................................................................... iii
List of Figures ........................................................................ iv
1 Introduction ........................................................................ 1
1.1 Features............................................................................... 2
1.2 Applications ......................................................................... 2
1.3 Specifications....................................................................... 3
1.4 Unpacking Checklist ............................................................ 5
1.5 Software Support ................................................................. 6
Programming library ....................................................... 6
DAQ-LVIEW PnP: LabVIEW® Driver ............................. 6
DAQBenchTM: ActiveX Controls .................................... 7
2 Hardware Information ........................................................ 9
2.1 Card Layout ......................................................................... 9
Bracket Layout .............................................................. 12
2.2 PCI-7442 Pin Assignments................................................ 13
CN2 Connector ............................................................. 13
CN1 Connector ............................................................. 15
2.3 PCI-7443 Pin Assignments................................................ 17
CN2 Connector ............................................................. 17
CN1 Connector ............................................................. 19
2.4 PCI-7444 Pin Assignments................................................ 21
CN2 Connector ............................................................. 21
CN1 Connector ............................................................. 23
2.5 TTL I/O Connector Pin Assignments ................................. 25
JP3 ............................................................................... 25
JP4 ............................................................................... 25
2.6 Board ID (S1)..................................................................... 26
3 Operation theory .............................................................. 27
3.1 Isolated digital input ........................................................... 27
3.2 Change of State (COS) interrupt ....................................... 28
Overview ....................................................................... 28
COS detection .............................................................. 28
COS detection architecture ........................................... 29
3.3 Isolated digital output channels ......................................... 30
3.4 Watchdog timer (WDT) ...................................................... 31
3.5 Programmable TTL Input/Output ....................................... 31