ADLINK PCI-7442 - Manual (Page 57)

Register Format 45
WDT INT Control, Hot-Reset, and Hold Control Register
There are two different interrupt modes in PCI-7442: the COS INT
function and the watch dog timer (WDT). You may enable the
WDT counter and let it count down as a mode of intrrupt. The
interrupt asserts when the watch dog timer counter counts to zero.
You can control WDT enable and clear WDT INT by setting two
bits (WDTE and WIC) in Bank2 WDT INT Control/Hot-Reset Hold
Control Register.
The PCI-7442 also provides some special safety functions indus-
trial applications. When the WDT interrupt asserts, you can set the
system to send out Safety DO value to prevent some untoward
damage by setting the SOE bit. When the system goes to an
unexpected or normal hot system reset without turning off the sys-
tem power, you can choose whether to allow the PCI-7442 board
to retain the original DO values before the system hot reset, or
allow the PCI-7442 board to enter the power-up initial procedure
to send out the default initial DO values which you configured.
Refer to Section 3.3 for details. By setting the HRHE bit, users can
enable Hot_Reset_Hold function anytime. This function is spe-
cially useful for unstable environments.
Address: BASE+0x8Ah
Reset Value: 0x0000h
Read/Write: W
-- -- -- -- WSOE WIC WDTE HRHE
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
-- -- -- -- -- -- -- --
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
Bit15 - 4 Not used
Bit0 HRHE: Hot Reset Hold Enable, enables hot-system-
reset DO hold function.
1: Enabled
0: Disabled
Bit1 WDTE: WDT interrupt enable/disable
1: Enabled
0: Disabled
Bit2 WIC: WDT interrupt clear