ADLINK ACL-8112 Series - Manual (Page 53)

Operation Theory • 45
5.4 Timer/Counter Operation
The ACL-8112 has an 8254 interval timer/counter onboard. Refer to section
3.5 for signal connection and the configuration of the counter.
The 8254 Timer / Counter Chip
The Intel (NEC) 8254 contains three independent, programmable, multi-
mode 16 bit counter/timers. The three independent 16 bit counters can be
clocked at rates from DC to 5MHz. Each counter can be individually
programmed with six different operating modes by appropriately formatted
control words. The most commonly uses for the 8254 in microprocessor
based systems are:
• programmable baud rate generator
• event counter
• binary rate multiplier
• real-time clock
• digital one-shot
• motor control
For more information about the 8254, please refer to the NEC
Microprocessors and peripherals or Intel Microsystems Components
Handbook.
Pacer Trigger Source
Counter 1 and 2 are cascaded together to generate a timer pacer trigger for
the A/D conversion. The frequency of the pacer trigger is software
controllable. The maximum pacer signal rate is 2MHz/4=500K which exceeds
the maximum A/D conversion rate of the ACL-8112. The minimum signal rate
is 2MHz/65535/65535, which is a very slow frequency that user may never
use.
General Purpose Timer/ Counter
Counter 0 is free for user applications. The clock source, gate control signal
and the output signal are sent via CN3. The general purpose timer/counter
can be used as an event counter, used for measuring frequency or other
functions. Please refer to 'Timer/Counter Applications' section for examples.