ADLINK ACL-8112 Series - Manual (Page 31)

Registers • 23
• CN 3: Analog Input/Output & Counter/Timer
(for differential connection:: ACL-8112DG/HG)
AIH2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
21
22
23
24
25
26
27
28
29
30
20
31
32
33
34
35
36
37
AIH3
AIH1
AIH0
AIH6
AIH7
AIH5
AIH4
A.GND
A.GND
V.REF
ExtRef2
A.GND
+12V
D.GND
N/C
+5V
ExtTrg
COUT0
CN3
AIL2
AIL1
AIL0
AIL5
AIL6
AIL4
AIL3
AO1
A.GND
AIL7
A.GND
ExtRef1
AO2
GATE0
GATE
N/C
ExtCLK
N/C
Figure 3.3b Pin Assignment of CN3
Note:
AIn: Analog Input Channel n (single-ended)
AIHn: Analog High Input Channel n (differential)
AILn: Analog Low Input Channel n (differential)
ExtRef n: External Reference Voltage for D/A CH n
AOn: Analog
Output Channel n
ExtCLK: External Clock Input
ExtTrig: External Trigger Signal
CLK: Clock input for 8254
GATE: Gate input for 8254
COUT n: Signal output of Counter n
V.ERF: Voltage Reference
A.GND: Analog Ground
GND: Ground