Cypress CY14B108L - Manual

ADVANCE
CY14B108L, CY14B108N
8-Mbit (1024K x 8/512K x 16) nvSRAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600
Document Number: 001-45523 Rev. *A Revised June 24, 2008
Features
■ 20 ns, 25 ns, and 45 ns access times
■ Internally organized as 1024K x 8 (CY14B108L) or 512K x 16
(CY14B108N)
■ Hands off automatic STORE on power down with only a small
capacitor
■ STORE to QuantumTrap ® nonvolatile elements initiated by
software, device pin, or AutoStore
®
on power down
■ RECALL to SRAM initiated by software or power up
■ Infinite read, write, and recall cycles
■ 200,000 STORE cycles to QuantumTrap
■ 20 year data retention
■ Single 3V +20%, –10% operation
■ Commercial and industrial temperatures
■ 48-pin FBGA, 44 and 54-pin TSOP II packages
■ Pb-free and RoHS compliance
Functional Description
The Cypress CY14B108L/CY14B108N is a fast static RAM, with
a nonvolatile element in each memory cell. The memory is
organized as 1024K words of 8 bits each or 512K words of 16
bits each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
A
0
- A
19
Address
WE
OE
CE
V
CC
V
SS
V
CAP
DQ0 - DQ7
HSB
CY14B108L
BHE
BLE
Logic Block Diagram
[1]
[1]
CY14B108N
Note
1. Address A
0
- A
19
and Data DQ0 - DQ7 for x8 configuration, Address A
0
- A
18
and Data DQ0 - DQ15 for x16 configuration.
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