Cypress CY7C1166V18 - Manual (Page 2)

CY7C1166V18, CY7C1177V18
CY7C1168V18, CY7C1170V18
Document Number: 001-06620 Rev. *D Page 2 of 27
Logic Block Diagram (CY7C1166V18)
Logic Block Diagram (CY7C1177V18)
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. D
e
code
Read Data Reg.
R/W
DQ
[7:0]
Output
Logic
Reg.
Reg.
Reg.
8
8
16
8
NWS
[1:0]
V
REF
W
rite Add. D
e
code
8
8
LD
Control
20
1M x 8
Array
1M x 8 Arr
a
y
Write
Reg Write
Reg
CQ
CQ
R/W
DOFF
QVLD
8
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. De
code
Read Data Reg.
R/W
DQ
[8:0]
Output
Logic
Reg.
Reg.
Reg.
9
9
18
9
BWS
[0]
V
REF
W
rite Add. De
code
9
9
LD
Control
20
1M x 9
Array
1M x 9 Arr
a
y
Write
Reg Write
Reg
CQ
CQ
R/W
DOFF
QVLD
9
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