Switching characteristics, Switching waveforms – Cypress CY62128B User Manual
Page 5
CY62128B
MoBL
®
Document #: 38-05300 Rev. *C
Page 5 of 11
Switching Characteristics
[7]
Over the Operating Range
Parameter
Description
62128B-55
62128B-70
Unit
Min.
Max.
Min.
Max.
READ CYCLE
t
RC
Read Cycle Time
55
70
ns
t
AA
Address to Data Valid
55
70
ns
t
OHA
Data Hold from Address Change
5
5
ns
t
ACE
CE
1
LOW to Data Valid, CE
2
HIGH to Data Valid
55
70
ns
t
DOE
OE LOW to Data Valid
20
35
ns
t
LZOE
OE LOW to Low Z
0
0
ns
t
HZOE
OE HIGH to High Z
[7, 9]
20
25
ns
t
LZCE
CE
1
LOW to Low Z, CE
2
HIGH to Low Z
[9]
5
5
ns
t
HZCE
CE
1
HIGH to High Z, CE
2
LOW to High Z
[8, 9]
20
25
ns
t
PU
CE
1
LOW to Power-up, CE
2
HIGH to Power-up
0
0
ns
t
PD
CE
1
HIGH to Power-down, CE
2
LOW to Power-down
55
70
ns
WRITE CYCLE
[10]
t
WC
Write Cycle Time
55
70
ns
t
SCE
CE
1
LOW to Write End, CE
2
HIGH to Write End
45
60
ns
t
AW
Address Set-up to Write End
45
60
ns
t
HA
Address Hold from Write End
0
0
ns
t
SA
Address Set-up to Write Start
0
0
ns
t
PWE
WE Pulse Width
45
50
ns
t
SD
Data Set-up to Write End
25
30
ns
t
HD
Data Hold from Write End
0
0
ns
t
LZWE
WE HIGH to Low Z
[9]
5
5
ns
t
HZWE
WE LOW to High Z
[8, 9]
20
25
ns
Switching Waveforms
Read Cycle No.1
[12, 13]
Notes:
7.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 100-pF load capacitance.
8.
t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured
±500 mV from steady-state voltage.
9.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
10. The internal write time of the memory is defined by the overlap of CE
1
LOW, CE
2
HIGH, and WE LOW. CE
1
and WE must be LOW and CE
2
HIGH to initiate a write,
and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates
the write.
11. No input may exceed V
CC
+ 0.5V.
12. Device is continuously selected. OE, CE
1
= V
IL
, CE
2
= V
IH
.
13. WE is HIGH for read cycle.
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
ADDRESS
DATA OUT