Cypress CY7C1410JV18 - Manual (Page 3)

CY7C1410JV18, CY7C1425JV18
CY7C1412JV18, CY7C1414JV18
Document #: 001-12561 Rev. *D Page 3 of 26
Logic Block Diagram (CY7C1412JV18)
Logic Block Diagram (CY7C1414JV18)
1M x 18 Arra
y CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
D
[17:0]
Read Add
. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
20
36
18
BWS
[1:0]
V
REF
W
rite Add. D
e
co
de
Write
Reg
18
A
(19:0)
20
CQ
CQ
DOFF
Q
[17:0]
18
18
18
Write
Reg
C
C
1M x 18 Arra
y
5
12K x 36
Array
CLK
A
(18:0)
Gen.
K
K
Control
Logic
Address
Register
D
[35:0]
Read
A
d
d. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
19
72
36
BWS
[3:0]
V
REF
W
rite Add.
Decode
Write
Reg
36
A
(18:0)
19
CQ
CQ
DOFF
Q
[35:0]
36
36
36
Write
Reg
C
C
5
12K x 36
Array
[+] Feedback