Switching characteristics – Cypress CY7C1410JV18 User Manual
Page 22
CY7C1410JV18, CY7C1425JV18
CY7C1412JV18, CY7C1414JV18
Document #: 001-12561 Rev. *D
Page 22 of 26
Switching Characteristics
Over the Operating Range
Cypress
Parameter
Consortium
Parameter
Description
267 MHz
250 MHz
Unit
Min
Max
Min
Max
t
POWER
V
DD
(Typical) to the first access
1
1
ms
t
CYC
t
KHKH
K Clock and C Clock Cycle Time
3.75
8.4
4.0
8.4
ns
t
KH
t
KHKL
Input Clock (K/K and C/C) HIGH
1.5
–
1.6
–
ns
t
KL
t
KLKH
Input Clock (K/K and C/C) LOW
1.5
–
1.6
–
ns
t
KHKH
t
KHKH
K Clock Rise to K Clock Rise and C to C Rise (rising edge to rising edge) 1.68
–
1.8
–
ns
t
KHCH
t
KHCH
K/K Clock Rise to C/C Clock Rise (rising edge to rising edge)
0
1.68
0
1.8
ns
Setup Times
t
SA
t
AVKH
Address Setup to K Clock Rise
0.3
–
0.35
–
ns
t
SC
t
IVKH
Control Setup to K Clock Rise (RPS, WPS)
0.3
–
0.35
–
ns
t
SCDDR
t
IVKH
DDR Control Setup to Clock (K/K) Rise (BWS
0
, BWS
1
, BWS
3
, BWS
4
)
0.3
–
0.35
–
ns
t
SD
t
DVKH
D
[X:0]
Setup to Clock (K/K) Rise
0.3
–
0.35
–
ns
Hold Times
t
HA
t
KHAX
Address Hold after K Clock Rise
0.3
–
0.35
–
ns
t
HC
t
KHIX
Control Hold after K Clock Rise (RPS, WPS)
0.3
–
0.35
–
ns
t
HCDDR
t
KHIX
DDR Control Hold after Clock (K/K) Rise (BWS
0
, BWS
1
, BWS
3
,BWS
4
)
0.3
–
0.35
–
ns
t
HD
t
KHDX
D
[X:0]
Hold after Clock (K/K) Rise
0.3
–
0.35
–
ns
Output Times
t
CO
t
CHQV
C/C Clock Rise (or K/K in Single Clock Mode) to Data Valid
–
0.45
–
0.45
ns
t
DOH
t
CHQX
Data Output Hold after Output C/C Clock Rise (Active to Active)
–0.45
–
–0.45
–
ns
t
CCQO
t
CHCQV
C/C Clock Rise to Echo Clock Valid
–
0.45
–
0.45
ns
t
CQOH
t
CHCQX
Echo Clock Hold after C/C Clock Rise
–0.45
–
–0.45
–
ns
t
CQD
t
CQHQV
Echo Clock High to Data Valid
–
0.27
–
0.30
ns
t
CQDOH
t
CQHQX
Echo Clock High to Data Invalid
–0.27
–
–0.30
–
ns
t
CQH
t
CQHCQL
Output Clock (CQ/CQ) HIGH
1.43
–
1.55
–
ns
t
CQHCQH
t
CQHCQH
CQ Clock Rise to CQ Clock Rise (rising edge to rising edge)
1.43
–
1.55
–
ns
t
CHZ
t
CHQZ
Clock (C/C) Rise to High-Z (Active to High-Z)
–
0.45
–
0.45
ns
t
CLZ
t
CHQX1
Clock (C/C) Rise to Low-Z
–0.45
–
–0.45
–
ns
DLL Timing
t
KC Var
t
KC Var
Clock Phase Jitter
–
0.20
–
0.20
ns
t
KC lock
t
KC lock
DLL Lock Time (K, C)
1024
–
1024
–
Cycles
t
KC Reset
t
KC Reset
K Static to DLL Reset
30
–
30
–
ns
Notes
20. When a part with a maximum frequency above 250 MHz is operating at a lower clock frequency, it requires the input timing of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
21. This part has a voltage regulator internally; t
POWER
is the time that the power is supplied above V
DD
minimum initially before a read or write operation can be initiated.
22. These parameters are extrapolated from the input timing parameters (t
KHKH
- 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (t
KC
Var) is already
included in the t
KHKH
). These parameters are only guaranteed by design and are not tested in production.
23. t
CHZ
, t
CLZ
, are specified with a load capacitance of 5 pF as in part (b) of
on page 21. Transition is measured ± 100 mV from steady
state voltage.
24. At any voltage and temperature t
CHZ
is less than t
CLZ
and t
CHZ
less than t
CO
.