Cypress CY7C1446AV33 - Manual (Page 22)

CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Document #: 38-05383 Rev. *E Page 22 of 31
Write Cycle Timing [26, 27]
Note:
27. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
X
LOW.
Switching Waveforms (continued)
tCYC
tCL
CLK
ADSP
tADH tADS
ADDRESS
tCH
OE
ADSC
CE
tAH tAS
A1
tCEH tCES
BWE,
BW X
Data Out (Q)
High-Z
ADV
BURST READ BURST WRITE
D(A2) D(A2 + 1) D(A2 + 1) D(A1) D(A3) D(A3 + 1) D(A3 + 2) D(A2 + 3)
A2 A3
Data In (D)
Extended BURST WRITE
D(A2 + 2)
Single WRITE
tADH tADS
tADH tADS
t
OEHZ
t
ADVH
t
ADVS
tWEH tWES
tDH tDS
GW
tWEH tWES
Byte write signals are
ignored for first cycle when
ADSP initiates burst
ADSC extends burst
ADV suspends burst
DON’T CARE UNDEFINED
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