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Identification register definitions, Scan register sizes, Identification codes – Cypress CY7C1446AV33 User Manual

Page 15

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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33

Document #: 38-05383 Rev. *E

Page 15 of 31

TAP DC Electrical Characteristics And Operating Conditions

(0°C < TA < +70°C; V

DD

= 3.135 to 3.6V unless otherwise noted)

[12]

Parameter

Description

Test Conditions

Min.

Max.

Unit

V

OH1

Output HIGH Voltage

I

OH

= –4.0 mA, V

DDQ

= 3.3V

2.4

V

I

OH

= –1.0 mA, V

DDQ

= 2.5V

2.0

V

V

OH2

Output HIGH Voltage

I

OH

= –100 µA

V

DDQ

= 3.3V

2.9

V

V

DDQ

= 2.5V

2.1

V

V

OL1

Output LOW Voltage

I

OL

= 8.0 mA

V

DDQ

= 3.3V

0.4

V

I

OL

= 1.0 mA

V

DDQ

= 2.5V

0.4

V

V

OL2

Output LOW Voltage

I

OL

= 100 µA

V

DDQ

= 3.3V

0.2

V

V

DDQ

= 2.5V

0.2

V

V

IH

Input HIGH Voltage

V

DDQ

= 3.3V

2.0

V

DD

+ 0.3

V

V

DDQ

= 2.5V

1.7

V

DD

+ 0.3

V

V

IL

Input LOW Voltage

V

DDQ

= 3.3V

–0.3

0.8

V

V

DDQ

= 2.5V

–0.3

0.7

V

I

X

Input Load Current

GND < V

IN

< V

DDQ

–5

5

µA

Identification Register Definitions

Instruction Field

CY7C1440AV33

(1M x 36)

CY7C1442AV33

(2M x 18)

CY7C1446AV33

(512K x 72)

Description

Revision Number (31:29)

000

000

000

Describes the version number.

Device Depth (28:24)

[13]

01011

01011

01011

Reserved for Internal Use

Architecture/Memory Type(23:18)

000000

000000

000000

Defines memory type and
architecture

Bus Width/Density(17:12)

100111

010111

110111

Defines width and density

Cypress JEDEC ID Code (11:1)

00000110100

00000110100

00000110100

Allows unique identification of
SRAM vendor.

ID Register Presence Indicator (0)

1

1

1

Indicates the presence of an ID
register.

Scan Register Sizes

Register Name

Bit Size (x36)

Bit Size (x18)

Bit Size (x72)

Instruction

3

3

3

Bypass

1

1

1

ID

32

32

32

Boundary Scan Order (165-ball FBGA package)

89

89

Boundary Scan Order (209-ball FBGA package)

138

Identification Codes

Instruction

Code

Description

EXTEST

000

Captures the I/O ring contents.

IDCODE

001

Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.

SAMPLE Z

010

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.

RESERVED

011

Do Not Use: This instruction is reserved for future use.

Notes:

12. All voltages referenced to V

SS

(GND).

13. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.

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