Cypress CY7C145 - Manual (Page 12)

CY7C145, CY7C144
Document #: 38-06034 Rev. *D Page 12 of 21
Figure 14. Busy Timing Diagram No. 1 (CE Arbitration) [29]
Figure 15. Busy Timing Diagram No. 2 (Address Arbitration) [29]
Note:
29. If t
PS
is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted
Switching Waveforms
(continued)
ADDRESS MATCH
t
PS
t
BLC
t
BHC
ADDRESS MATCH
t
PS
t
BLC
t
BHC
ADDRESS
L,R
BUSY
R
CE
L
CE
R
BUSY
L
CE
R
CE
L
ADDRESS
L,R
CE
L
Valid First:
CE
R
Valid First:
ADDRESS MATCH
t
PS
ADDRESS
L
BUSY
R
ADDRESS MISMATCH
t
RC
or t
WC
t
BLA
t
BHA
ADDRESS
R
ADDRESS MATCH ADDRESS MISMATCH
t
PS
ADDRESS
L
BUSY
L
t
RC
or t
WC
t
BLA
t
BHA
ADDRESS
R
Left Address Valid First:
Right Address Valid First:
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