Kontron VM62 - Manual (Page 62)

Chapter 6 Software Configuration VM62(A) / VM42(A) User’s Manual
Address List of Involved Registers
MBAR 0x3FF00 (CPU space!)
R S R 0xC0001009
S Y P C R 0xC0001022
M C R 0xC0001000
PLLCR 0xC0001010
C D V C R 0xC0001014
CLKOCR 0xC000100C
P E P A R 0xC0001016
GMR 0xC0001040
A V R 0xC0001008
B R 0 0xC0001050
O R 0 0xC0001054
B R 1 0xC0001060
O R 1 0xC0001064
B R 2 0xC0001070
O R 2 0xC0001074
B R 3 0xC0001080
O R 3 0xC0001084
B R 4 0xC0001090
O R 4 0xC0001094
B R 5 0xC00010A0
O R 5 0xC00010A4
B R 6 0xC00010B0
O R 6 0xC00010B4
B R 7 0xC00010C0
O R 7 0xC00010C4
CICR 0xC0001540
S D C R 0xC000151E
V C S R 0xCD000005
B C S R 0xCD000007
6.2 Initialising the Cache
Before the system enables any cache present, they should be invalidated using:
cinva bc
Furthermore, the complete address range should not be cachable, as caching only makes sense on DRAM and FLASH
EPROM. Other areas should never be cached and must be switched to serialised in order to prevent the
MC68040/MC68060 from mixing up read and write cycles.
The easiest way of doing this is to make use of the DTT0 register, in the following way:
move.l #$807FE040,d1
movec d1,dtt0
The code above sets all addresses below $80000000 to cacheable and non-serialised, whereas all addresses above are set to
non-cacheable and serialised.
Accesses to the DRAM and FLASH should be made at $0 and $4000000. All other components addressed by the
MC68EN360 should always be accessed over the mirrored area with $Cxxxxxxx, as described in Section 2.2.5 Address
Map.
Page 6-4 ©1995 PEP Modular Computers May 17, 1996