Kontron VM62 - Manual (Page 33)

Chapter 2 Functional Description VM62(A) / VM42(A) User’s Manual
Note
During VMEbus cycles, the on-board bus error timer is reset as soon as the VM62(A) / VM42(A) gains
VMEbus ownership. This means that the time gap between a VMEbus request and the starting of the
VMEbus cycle is monitored by the on-board BERR timer. VMEbus cycles themselves are monitored
by the separate VMEbus BERR timer (BUS monitor).
2.6.5 VME Bus Error Timer
The VM62(A) / VM42(A) also provides a bus monitor for the VMEbus. A 128
µ
s timeout timer monitors VMEbus data
transfer cycle lengths and generates a VMEbus BERR* signal for error termination. This timer is enabled/disabled via the
VME control/status register which also supplies a timeout status bit in order to identify bus errors generated by the bus
monitor.
2.6.6 Watchdog Timer
A 512ms watchdog timer triggers the on-board and VME system reset generator at timeout. Once enabled via the board
control/status register, the watchdog timer cannot be reset by software. It must be re-triggered via the corresponding bit in
the board control/status register periodically within the timeout period. ‘Watchdog timer running’ is a status that is
displayed by the yellow front panel LED.
Figure 2.6.6.1: Watchdog LED Location
W
Watchdog LED
Yellow
2.6.7 First Slot Detection (FSD)
The VM62(A)/VM62(A) detects during power-up whether the CPU in use is positioned in the far left slot of the system.
This is achieved using a 100k pull-down resistor at the BG3IN* pin.
BG3IN* low = system controller (far left slot)
BG3IN* high = no system controller
This information can be read from the VMEbus Control/Status register and is valid until the next power down of the
system.
Page 2-18 © 1995 PEP Modular Computers May 17, 1996