Kontron VM62 - Manual (Page 20)

VM62(A) / VM42(A) User’s Manual Chapter 2 Functional Description
2.2.6 DMA Transfers
Memory to memory transfers with the 68EN360 DMAs are possible with any combination of on-board and VME
addresses. In order to achieve address compatibility between CPU/VME and DMA/VME transfers, it is recommended that
the initialisation of CS2 be initialised to the standard VME address space as described in the Software Configuration
chapter in this manual.
2.3 VMEbus Interface
The VM62(A) / VM42(A) has a complete master interface for the P1, J1 VMEbus connector. It consists of a VMEbus
arbiter, requester, system controller and buffers for data/address/control signals. In addition, the VM62(A) / VM42(A)
provides a VMEbus slave interface which consists of a programmable board address decoder, a dual-ported RAM and a
mailbox interrupt controller.
2.3.1 System Controller
The VM62(A) / VM42(A) can act as a VME system controller with arbiter, system clock driver, power monitor with
system reset driver, IACK daisy chain driver and 7-level VMEbus interrupt controller.
Arbitration is single level FAIR 1 on BR3*. If the VM62(A) / VM42(A) is used as system controller it has to be placed
in slot 1 of the VMEbus backplane (furthermost left slot). There is no jumper setting necessary, as the board provides a
‘first slot detection’ function which is also readable within the VME control / status register. The IACK daisy chain
driver is supplied by connecting the IACKIN* and IACKOUT* line. IACK* is connected via the VMEbus backplane for
IACKIN* of slot 1.
VME SYSCLK* and SYSRES* can be routed from on-board using jumpers, leaving the choice of generating these
signals by the system controller to the user. SYSFAIL* generates a maskable on-board autovectored interrupt (see also
External Autovector Requests). ACFAIL* generates a non-maskable autovector level 7 interrupt (NMI) in the same way
as the ABORT button. When an ACFAIL* NMI is detected, it can be differentiated from an ABORT by reading bit 1 of
the Board Control/Status Register (bit 1 is set to ‘1’ for ACFAIL*). If this is the case, the CPU should stay in the IRQ
service routine and save any important data to non-volatile memory.
The VM62(A) / VM42(A) also provides a bus monitor for the VMEbus. A 128
µ
s timeout timer monitors VMEbus data
transfer cycle lengths and generates a VMEbus BERR* signal for error termination. This timer is enabled/disabled via the
VME control / status register which also supplies a timeout status bit in order to identify bus errors generated by the bus
monitor.
2.3.2 Dual-Ported SRAM
The VM62(A) / VM42(A) provides on-board SRAM of either 256 kByte or 1 Mbyte. The SRAM is 16- bit wide and
dual-ported between the CPU/DMA and VME, accessible through an on-board arbiter. Read-Modify-Write cycles (TAS
instruction used for semaphores) are supported in any direction. The location of the dual-ported SRAM as seen from the
VME is programmable via the VME control / status register. There are 16 different base addresses possible that are all
located in the VME standard supervisor / user data space. Enable / disable is selected using a separate bit.
Note
The lower 8 kBytes of dual-ported SRAM should not be accessed from the VME because this area is
reserved for mailbox interrupts.
1 FAIR according to VME 64 Specifications, Rule 3.14 and Observation 3.17.
May 17, 1996 © 1995 PEP Modular Computers Page 2-5