Kontron CP384 - Manual (Page 55)

ID 31440, Rev. 01 Kontron Modular Computers GmbH
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Configuration CP384
4.4.2 Reading Input Data
The input ports are made visible via the Input Data Register. This register reflects the inputs
after them having passed the digital programmable debouncer. An active input appears there
as a logical "1" whereas an open or inactive input port appears as a logical "0". The bit ordering
naturally corresponds with the numbering of the input ports at the connector.
4.4.3 Debouncing Inputs
By default, all inputs are filtered through a passive analog low-pass filter placed immediately
behind the input connector. Additionally, the CP384 provides a programmable digital debounc-
er which is common for all inputs. The input ports are sampled at a programmable sample rate
which is derived from PCI bus clock. Two consecutive samples must be equal before being
stored in the input data register. By this means, bouncing and spikes on inputs can be filtered
out. For example, with a selected input sample rate of 500 Hz, input pulses which are shorter
than 2 ms are filtered out.
Table 4-2: Input Data Register
BITS TYPE DEFAULT FUNCTION
31-16 r 0 Reserved
15-0 r - Input (debounced)
Note ...
Where the enhanced features such as interrupts, pattern or event detection are
not required, only the input data register is relevant.
Table 4-3: Transparent Input Data Register
BITS TYPE DEFAULT FUNCTION
31-16 r 0 Reserved
15-0 r - Input (transparent)
Note ...
In addition to the Input Data Register, there is a second non-latched input regis-
ter (debouncer bypassed).
Table 4-4: Input Control Register
BITS TYPE DEFAULT FUNCTION
31-8 R/W 0 RESERVED
7 r/w 0 Input enable
6 r/w 0 Event detect enable
5 r/w 0 Latch mode enable
4 r/w 0 Pattern detect enable
3 r/w 0 Reserved
2-0 r/w 000 Debounce control deb [2 ... 0]