Achronix Speedster22i Pin Connections and Power Sequencing - Manual (Page 13)

UG042, August 19, 2014 13
Revision History
The following table shows the revision history for this document.
Date Version Revisions
04/05/2013 1.0 Initial Achronix release.
04/12/2013 1.1 Reduced unique power supply requirements.
04/16/2013 1.2 Clarified connection requirements for some SerDes pins.
04/29/2013 1.3 Corrected connection scheme and pull up value (1.8V) for configuration pins
05/17/2013 1.4 Updated multiple entries in the pin connections to align with pin table.
06/11/2013 1.5 Additional information on some config I/Os and made User I/O section more concise.
07/26/2013 1.6 Clarifications for the CONFIG_STATUS and CONFIG_DONE I/Os.
10/17/2013 1.7 VDD_CFGWL update and CONFIG_RSTN assertion requirement during power-up.
11/07/2013 1.8 Modified JTAG/STAP_SEL, VDD_CFGWL and eFuse power supply requirements.
04/24/2014 1.9 Updated PCIe Gen3 requirements, sense lines and I/O power rail needs.
07/17/2014 1.10
Updated regulator needs for VDD_CFGWL and VREFs. Expanded explanations for
other power supplies, and changed pull-up needs for some config pins.
08/19/2014 1.11 Updated SCK spec, JTAG TRSTN and corrected power supply block diagram.