Achronix Speedster22i Pin Connections and Power Sequencing - Manual (Page 12)

12 UG042, August 19, 2014
Power Sequencing Block Diagram
Power Up Requirements
VCC, VDD_CFG, VDD_BRAM
VDD_CFGWL
VDDO_B[xx] (1.2V/1.5V/1.8V)
VDDO_JCFG
AVDD_PLL
VDDA_NOM_E/W
VCCRAM/FHV_EFUSE
PA_VDD1
PA_VDD2
Begin powering up
PA_VDD1 and
PA_VDD2 after VCC
is fully powered-up
Power these down
before the other
supplies
Config_status
VDDL
Begin powering up VDDL after
Config_status goes high
Power Down Requirements
VCC, VDD_CFG, VDD_BRAM
VDD_CFGWL
VDDO_B[xx] (1.2V/1.5V/1.8V)
VDDO_JCFG
AVDD_PLL
VDDA_NOM_E/W
VCCRAM/FHV_EFUSE
PA_VDD1
PA_VDD2
Config_status
VDDL
Config_rstn
Config_rstn
Assert config reset after
VCC, PA_VDD1/2
come up
Config_status released
some time after device
comes out of reset