Cypress SL811HS - Manual (Page 26)

SL811HS
Document 38-08008 Rev. *D Page 26 of 32
Bus Interface Timing Requirements
I/O Write Cycle
Note nCS an be held LOW for multiple Write cycles provided nWR is cycled. Write Cycle Time for Auto Inc Mode Writes is 170
ns minimum.
nWR
A0
D0-D7 DATA
twr
twahld
twdhld
twasu
twdsu
twdsu
twdhld
I/O Write Cycle to Register or Memory Buffer
Register or Memory
Address
nCS
twcsu twshld
Tcscs See Note.
twrhigh
Parameter Description Min. Typ. Max.
t
WR
Write pulse width 85 ns
t
WCSU
Chip select set-up to nWR LOW 0 ns
t
WSHLD
Chip select hold time
After nWR HIGH 0 ns
t
WASU
A0 address set-up time 85 ns
t
WAHLD
A0 address hold time 10 ns
t
WDSU
Data to Write HIGH set-up time 85 ns
t
WDHLD
Data hold time after Write HIGH 5 ns
t
CSCS
nCS inactive to nCS* asserted 85 ns
t
WRHIGH
NWR HIGH 85 ns