Cypress CY7C1387DV25 - Manual (Page 22)

CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25
Document Number: 38-05548 Rev. *E Page 22 of 30
Write Cycle Timing [26, 27]
Switching Waveforms (continued)
t CYC
tCL
CLK
ADSP
tADH tADS
ADDRESS
tCH
OE
ADSC
CE
tAH tAS
A1
tCEH tCES
BWE,
BW X
ADV
BURST READ BURST WRITE
D(A2) D(A2 + 1) D(A3) D(A3 + 1) D(A2 + 3)
A2 A3
Extended BURST WRITE Single WRITE
tADH tADS
tADH tADS
t
OEHZ
tADVH tADVS
tWEH tWES
t
DH
t
DS
GW
tWEH tWES
Byte write signals are ignored for first cycle when
ADSP initiates burst
ADSC extends burst
ADV suspends burst
DON’T CARE UNDEFINED
D(A1) High-Z Data in (D)
Data Out (Q)
Note
27. Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW and BW
X
LOW.
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