Cypress CY7C1387DV25 - Manual (Page 21)

CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25
Document Number: 38-05548 Rev. *E Page 21 of 30
Switching Waveforms
Read Cycle Timing [26]
tCYC
tCL
CLK
ADSP
tADH tADS
ADDRESS
tCH
OE
ADSC
CE
tAH tAS
A1
tCEH tCES
GW, BWE,BW
Data Out (DQ) High-Z
tDOH
tCO
ADV
tOEHZ
tCO
Single READ BURST READ
tOEV
tOELZ tCHZ
Burst wraps around
to its initial state
tADVH tADVS
tWEH tWES
tADH tADS
Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A1) Q(A2) Q(A2 + 1) Q(A3) Q(A2 + 3)
A2 A3
Deselect
cycle
Burst continued with
new base address
ADV suspends burst
DON’T CARE UNDEFINED
X
CLZ
t
Note
26. On this diagram, when CE is LOW, CE
1
is LOW, CE
2
is HIGH and CE
3
is LOW. When CE is HIGH, CE
1
is HIGH or CE
2
is LOW or CE
3
is HIGH.
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