Cypress STK11C68-5 - Manual (Page 7)

STK11C68-5 (SMD5962-92324)
Document Number: 001-51001 Rev. *A Page 7 of 15
Figure 7. SRAM Read Cycle 2: CE and OE Controlled [4]
AC Switching Characteristics
SRAM Read Cycle
Parameter
Description
35 ns 45 ns 55 ns
Unit
Min Max Min Max Min Max
Cypress
Parameter
Alt
t
ACE
t
ELQV
Chip Enable Access Time 35 45 55 ns
t
RC
[4] t
AVAV,
t
ELEH
Read Cycle Time 35 45 55 ns
t
AA
[5] t
AVQV
Address Access Time 35 45 55 ns
t
DOE
t
GLQV
Output Enable to Data Valid 15 20 35 ns
t
OHA
[5] t
AXQX
Output Hold After Address Change 5 5 5 ns
t
LZCE
[6] t
ELQX
Chip Enable to Output Active 5 5 5 ns
t
HZCE
[6] t
EHQZ
Chip Disable to Output Inactive 13 15 25 ns
t
LZOE
[6] t
GLQX
Output Enable to Output Active 0 0 0 ns
t
HZOE
[6] t
GHQZ
Output Disable to Output Inactive 13 15 25 ns
t
PU
[3] t
ELICCH
Chip Enable to Power Active 0 0 0 ns
t
PD
[3] t
EHICCL
Chip Disable to Power Standby 35 45 55 ns
Switching Waveforms
Figure 6. SRAM Read Cycle 1: Address Controlled
[4, 5]
Notes
4. WE must be High during SRAM Read cycles.
5. I/O state assumes CE and OE < V
IL
and WE > V
IH
; device is continuously selected.
6. Measured ± 200 mV from steady state output voltage.
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