Cypress CY7C1380FV25 - Manual (Page 21)

CY7C1380DV25, CY7C1380FV25
CY7C1382DV25, CY7C1382FV25
Document #: 38-05546 Rev. *E Page 21 of 29
Write Cycle Timing [25, 26]
Switching Waveforms (continued)
t CYC
tCL
CLK
ADSP
tADH tADS
ADDRESS
tCH
OE
ADSC
CE
tAH tAS
A1
tCEH tCES
BWE,
BW X
Data Out (Q)
High-Z
ADV
BURST READ BURST WRITE
D(A2) D(A2 + 1) D(A2 + 1) D(A1) D(A3) D(A3 + 1) D(A3 + 2) D(A2 + 3)
A2 A3
Data In (D)
Extended BURST WRITE
D(A2 + 2)
Single WRITE
tADH tADS
tADH tADS
t
OEHZ
t
ADVH
t
ADVS
tWEH tWES
tDH tDS
GW
tWEH tWES
Byte write signals are
ignored for first cycle when
ADSP initiates burst
ADSC extends burst
ADV suspends burst
DON’T CARE UNDEFINED
Note:
26. Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW and BW
X
LOW.
[+] Feedback