Cypress Perform CY7C1380F - Manual (Page 24)

CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Document #: 38-05543 Rev. *F Page 24 of 34
Figure 11. Write Cycle Timing [26, 27]
Switching Waveforms
(continued)
t CYC
tCL
CLK
ADSP
tADH tADS
ADDRESS
tCH
OE
ADSC
CE
tAH tAS
A1
tCEH tCES
BWE,
BW X
ata Out (Q)
High-Z
ADV
BURST READ BURST WRITE
D(A2) D(A2 + 1) D(A2 + 1) D(A1) D(A3) D(A3 + 1) D(A3 + 2) D(A2 + 3)
A2 A3
Data In (D)
Extended BURST WRITE
D(A2 + 2)
Single WRITE
tADH tADS
tADH tADS
t
OEHZ
t
ADVH
t
ADVS
tWEH tWES
tDH tDS
GW
tWEH tWES
Byte write signals are
ignored for first cycle when
ADSP initiates burst
ADSC extends burst
ADV suspends burst
DON’T CARE UNDEFINED
Note
27. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
X
LOW.
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