Cypress CY14B104LA - Manual (Page 15)

PRELIMINARY
CY14B104LA, CY14B104NA
Document #: 001-49918 Rev. *A Page 15 of 23
Hardware STORE Cycle
Parameters Description
20 ns 25 ns 45 ns
Unit
Min Max Min Max Min Max
t
DHSB
HSB To Output Active Time when write latch not set 20 25 25 ns
t
PHSB
Hardware STORE Pulse Width 15 15 15 ns
t
SS
[26, 27] Soft Sequence Processing Time 100 100 100
μs
Switching Waveforms
Figure 14. Hardware STORE Cycle
[20]
Figure 15. Soft Sequence Processing
[26, 27]
t
PHSB
t
PHSB
t
DELAY
t
DHSB
t
DELAY
t
STORE
t
HHHD
t
LZHSB
Write latch set
Write latch not set
HSB (IN)
HSB (OUT)
DQ (Data Out)
RWI
HSB (IN)
HSB (OUT)
RWI
HSB pin is driven high to V
CC
only by Internal
SRAM is disabled as long as HSB (IN) is driven low.
HSB driver is disabled
t
DHSB
100kOhm resistor,
Address #1 Address #6 Address #1 Address #6
Soft Sequence
Command
t
SS
t
SS
CE
Address
V
CC
t
SA
t
CW
Soft Sequence
Command
t
CW
Notes
26. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
27. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
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