Cypress CY14B104LA - Manual (Page 12)

PRELIMINARY
CY14B104LA, CY14B104NA
Document #: 001-49918 Rev. *A Page 12 of 23
Figure 9. SRAM Write Cycle #2: CE Controlled [3, 16, 17, 18]
Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled [3, 16, 17, 18]
Data Output
Data Input Input Data Valid
High Impedance
Address Valid Address
t
WC
t
SD
t
HD
BHE, BLE
WE
CE
t
SA
t
SCE
t
HA
t
BW
t
PWE
Data Output
Data Input Input Data Valid
High Impedance
Address Valid Address
t
WC
t
SD
t
HD
BHE, BLE
WE
CE
t
SCE
t
SA
t
BW
t
HA
t
AW
t
PWE
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