Cypress CY7C1364C - Manual (Page 12)

CY7C1364C
Document #: 38-05689 Rev. *E Page 12 of 18
Switching Waveforms
Read Cycle Timing
[18]
Note:
18. On this diagram, when CE is LOW, CE
1
is LOW, CE
2
is HIGH and CE
3
is LOW. When CE is HIGH, CE
1
is HIGH or CE
2
is LOW or CE
3
is HIGH.
tCYC
t
CL
CLK
ADSP
t
ADH
t
ADS
ADDRESS
t
CH
OE
ADSC
CE
tAH tAS
A1
tCEH tCES
GW, BWE,
BW[A:D]
Data Out (Q) High-Z
tCLZ
tDOH
tCO
ADV
tOEHZ
tCO
tOEV
tOELZ tCHZ
ADV
suspends
burst.
Burst wraps around
to its initial state
tADVH tADVS
tWEH tWES
tADH tADS
Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A1) Q(A2) Q(A2 + 1) Q(A2 + 3)
A2 A3
Deselect
cycle
Burst continued with
new base address
[+] Feedback