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Cypress CY62138FV30 User Manual

Mbit (256k x 8) static ram, Features, Functional description

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Cypress Semiconductor Corporation

198 Champion Court

San Jose

,

CA 95134-1709

408-943-2600

Document #: 001-08029 Rev. *E

Revised March 26, 2007

CY62138FV30 MoBL

®

2-Mbit (256K x 8) Static RAM

Features

• Very high speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin compatible with CY62138CV25/30/33
• Ultra low standby power

— Typical standby current: 1

µA

— Maximum standby current: 5

µA

• Ultra low active power

— Typical active current: 1.6 mA @ f = 1 MHz

• Easy memory expansion with CE

1

, CE

2,

and OE features

• Automatic power down when deselected
• CMOS for optimum speed and power
• Offered in Pb-free 36-ball VFBGA, 32-pin TSOP II, 32-pin

SOIC, 32-pin TSOP I and 32-pin STSOP packages

Functional Description

[1]

The CY62138FV30 is a high performance CMOS static RAM

organized as 256K words by 8 bits. This device features

advanced circuit design to provide ultra low active current.

This is ideal for providing More Battery Life™ (MoBL

®

) in

portable applications such as cellular telephones. The device

also has an automatic power down feature that significantly

reduces power consumption. Place the device into standby

mode reducing power consumption when deselected (CE

1

HIGH or CE

2

LOW).

To write to the device, take Chip Enable (CE

1

LOW and CE

2

HIGH) and Write Enable (WE) inputs LOW. Data on the eight

IO pins (IO

0

through IO

7

) is then written into the location

specified on the address pins (A

0

through A

17

).

To read from the device, take Chip Enable (CE

1

LOW and CE

2

HIGH) and Output Enable (OE) LOW while forcing Write

Enable (WE) HIGH. Under these conditions, the contents of

the memory location specified by the address pins appear on

the IO pins.
The eight input and output pins (IO

0

through IO

7

) are placed

in a high impedance state when the device is deselected (CE

1

HIGH or CE

2

LOW), the outputs are disabled (OE HIGH), or

during a write operation (CE

1

LOW and CE

2

HIGH and WE

LOW).

Logic Block Diagram

A0

IO0

IO7

IO1
IO2
IO3
IO4
IO5
IO6

A1

A2

A3

A4

A5

A6

A7

A8

A9

SENSE AMPS

POWER

DOWN

WE

OE

A

13

A

14

A

15

A

16

ROW DECODER

COLUMN DECODER

256K x 8

ARRAY

DATA IN DRIVERS

A10

A11

A

17

CE1

CE2

A

12

Note

1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at

http://www.cypress.com.

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