Cirrus Logic CS61584A - Manual (Page 24)

CS61584A
24 DS261PP5
DS261PP5
Latched-LOS: Set high on the rising edge of the
loss of signal condition. Reading the Status register
clears the Latched-LOS bit and deactivates the INT
pin. Refer to the timing diagram in Figure 18.
AIS: Set high while the alarm indication signal is
detected. Reading the Status register does not clear
the AIS bit. An AIS interrupt is generated only on
the falling edge of the AIS alarm condition. The
Latched-AIS bit generates an interrupt on the rising
edge of AIS. Refer to the timing diagram in
Figure 18.
Status Register (Channel 1)
Serial Port Address: 0x10; Parallel Port Address: 0xY0
Bit Description Definition Reset
Value 1 0
7 LOS1 LOS currently detected no LOS 1
6 Latched-LOS1 LOS event since last read no LOS 1
5 AIS1 AIS currently detected no AIS 0
4 Latched-AIS1 AIS event since last read no AIS 0
3 Latched-BPV1 BPV event since last read no BPV 0
2 Latched-Overflow1 Pulse overflow since last read no overflow 0
1 Latched-Reset Reset event since last read no reset 1
0 Interrupt1 Interrupt event since last read no interrupt 1
Status Register (Channel 2)
Serial Port Address: 0x11; Parallel Port Address: 0xY1
Bit Description Definition Reset
Value 1 0
7 LOS2 LOS currently detected no LOS 1
6 Latched-LOS2 LOS event since last read no LOS 1
5 AIS2 AIS currently detected no AIS 0
4 Latched-AIS2 AIS event since last read no AIS 0
3 Latched-BPV2 BPV event since last read no BPV 0
2 Latched-Overflow2 Pulse overflow since last read no overflow 0
1 Latched-CLKLOST TCLK or REFCLK absent TCLK and REFCLK present 0
0 Interrupt2 Interrupt event since last read no interrupt 1
Table 5. Status Registers
AIS/LOS Currently Active
(AIS/LOS bit & AIS/LOS pin)
Latched LOS
(Latch AIS/LOS bit)
Read AIS/LOS bits
"Short" AIS/LOS event "Long" AIS/LOS event
Set by start
of AIS/LOS
Cleared by read
Set by Change
of AIS/LOS
Cleared by read
Interrupt
(INT)
Figure 18. Alarm Indication Event Relationships
CS61584A
24 DS261F1